20V8 / PALCE20V8H-25JC4 / PALCE20V8H / flash erasable

What is for sale: 20V8 / PALCE20V8H-25JC4 / PALCE20V8H / flash erasable

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Please note: These parts are new with a factory program.
EE CMOS 24-Pin Universal Programmable Array Logic
Pin and function compatible with all GAL 20V8/As
Electrically erasable CMOS technology provides reconfigurable logic and full testability
* — 5-ns propagation delay for “-5” version
* — 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for a wide range of 24-pin PAL devices
Programmable enable/disable control
Outputs individually programmable as registered or combinatorial
Peripheral Component Interconnect (PCI) compliant
Preloadable output registers for testability
Automatic register reset on power-up
Extensive third-party software and programmer support through FusionPLD partners
Fully tested for 100% programming and functional yields and high reliability
5-ns version utilizes a split leadframe for improved performance
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the user’s design specification. A design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming file based on Boolean or state equations. Design software also verifies the design and can provide test vectors for the finished device. Programming can be accomplished on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically.